1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device that uses a variable resistive element the resistance value of that varies by applying a voltage with respect thereto and a driving method for the non-volatile semiconductor memory device.
2. Description of the Related Art
Conventionally, a NAND type flash EEPROM is known as an EEPROM (Electrically Erasable and Programmable Read Only Memory) with respect to that high degree of integration can be performed. A memory transistor of the NAND type flash EEPROM has a stacked-gate structure wherein, on the semiconductor substrate, an electric-charge accumulation layer (floating gate) and a control gate are formed in the way of their being stacked with an insulating film in between. An example of the NAND type flash EEPROM is illustrated in FIGS. 15 to 18. FIG. 15 is an equivalent circuit diagram illustrating a memory array of the NAND type flash EEPROM; FIG. 16 is a plan view illustrating a layout corresponding to the circuit illustrated in FIG. 15; and FIG. 17 is a sectional view illustrating a layout taken along a line A–A′ of FIG. 16. In FIG. 15, MC0 to MC31 represent memory cells; BL0 to BL4223 represent bit lines; WL0 to WL 31 represent word lines; SSTs and GSTs represent selection transistors; and SSL and GSL respectively represent selection signals with respect to the selection transistors SST and GST. In FIGS. 16 and 17, a reference numeral 19 denotes a metal wiring layer; a reference numeral 15 denotes a floating gate; a reference numeral 17 denotes a control gate serving as a word line; a reference numeral 14 denotes a tunnel oxide film; reference numerals 16 and 18 denote inter-layer gate insulating films, respectively; reference numerals 21, 21a, and 21b each denote a source or drain region of the memory cells MC0 to MC 31; a reference numeral 10 denotes a p-type silicon substrate; a reference numeral 11 denotes an n-type well; a reference numeral 12 denotes a p-type well; and a reference numeral 13 denotes a for-elemental-isolation insulating film. Like this, as illustrated in, for example, FIG. 15, the NAND type flash EEPROM is made up into a structure wherein, for example, 32 pieces of memory cells MC0 to MC31 are arranged in series and, at both ends of the arrangement, there are disposed the selection transistors SST and GST. For this reason, as illustrated in FIGS. 16 and 17, adjoining two of the memory cell transistors can share a source, or a drain region and therefore it is possible to greatly reduce the memory size per bit and thereby to suppress the increase in the chip area. Like this, the NAND type flash EEPROM has the greatest feature as a large capacity file memory that its cell size is small and that therefore the bit cost is low.
The memory cell transistor performs non-volatile storage therein of data in dependence upon the state of its floating gate in which electric charge is accumulated. Specifically, setting, for example, as data “0” the high-threshold voltage state of floating gate in which electrons have been injected from a relevant channel and as data “1” the low-threshold voltage state of floating gate in which electrons therein have been discharged into the channel, storage of 2-level data is performed. Recently, multi-level storage such as storage of 4-level data has also been performed by more finely controlling the distribution of the threshold values.
Here, the programming operation of the NAND type EEPROM will be explained with reference to FIG. 18. It is to be noted that, in the following description, a plurality of memory cells that are connected in series are referred to as “the block”. When programming data, the data within the NAND-cell block is collectively erased in advance. This is executed by applying an earth potential Vss to all control gate lines WL0 to WL31 (word lines), then applying an increased level of positive erasing voltage Vera (for example an erasing pulse of 3 milliseconds and 21V) to the p-type well region (12 in FIG. 17) of the cell array, and thereby discharging the electrons accumulated in the floating gate into the relevant channel. As a result of this, all data within the NAND-cell block is brought to a state of “1” (a state of being erased). Writing data, after the above-described collective erasure has been performed, is collectively executed with respect to a plurality of memory transistors (this region is ordinarily called “1 page”) that are connected along the control gate line, sequentially selected from the source side.
In the programming operation, to the word line (here WL17) that has been selected there is applied an increased level of positive voltage Vpgm; to the unselected word lines (WL0 to WL16 and WL18 to WL31) that have not been selected there is applied an intermediate potential Vpass; to the selected gate line SSL for the bit lines (BL0 and BL1) there is applied a voltage Vcc; and to the selected gate line GSL on the common source SL side there is applied a voltage Vss (=0V). Also, to the bit line BL0 with respect to which data “0” is to be written there is applied a voltage Vss while, on the other hand, to the bit line BL1 with respect to which data “1” is to be programmed or in a state of data's programming inhibited for maintaining an erased state there is applied a voltage Vcc.
At this time, in the selected memory cell MC 170 that is connected to the bit line BL0 that has been applied with a voltage Vss, the potential of the channel is maintained at the level of Vss and a high magnitude of electric field is applied between the control gate that has been applied with the voltage of Vpgm and the channel region. As a result of this, the phenomenon of the electrons' being injected from the channel region to the floating gate due to the tunnel current occurs. However, in the other unselected memory cells that are connected to the same bit line BL0 and that have been applied with the intermediate potential of Vpass, a sufficiently high magnitude of electric field is not applied thereto. Therefore, programming data is not executed there.
On the other hand, the memory cells that are located along the bit line BL1 that has been applied with the voltage of Vcc become cut off as a result of the channel region's of the NAND cell being preliminarily charged to a voltage of Vcc or Vcc−Vth (the Vth represents the threshold voltage of the selected memory cell). And, owing to the series capacitive coupling prepared using the control gate 17, floating gate 15, channel region, and p-type well 12, the control gates being applied with the programming voltage Vpgm and intermediate voltage Vpass, the potential of the channel region gets increased. This obstructs the occurrence of the phenomenon that the electrons are injected from the channel into the floating gate.
In the above-described way, injection of the electrons into the floating gate occurs only in the memory cell M170 at the portion of intersection of the bit line BL0 applied with the voltage Vss and the selected word line WL 17 applied with the voltage Vpgm. As a result of this, programming data “0” into any of the other memory cells is inhibited. In contrast, in the programming-inhibited memory cells within the selected block, as described above, the potential of the channel is determined depending on the capacitive coupling between the word line and the channel region of the NAND cell. However, in case of the NAND type flash EEPROM, the movement of the electric charge that follows the programming and erasing operations takes place due to the FN (Fowler-Nordheim) tunnel phenomena. Therefore, the programming/erasing length of time is as unsuitable, as given in milliseconds, to the application requiring the execution of high-speed programming and erasure.
As another example using a NAND type cell array structure such as that described above there is disclosed in the specification of, for example, U.S. Pat. No. 6,331,943 a NAND type Magnetic Random Access Memory (NAND type MRAM) with a structure wherein a plurality of memory cells each having a magnetic resistive element and a MOS transistor connected thereto in parallel are connected in series; and a selection gate is disposed at least one of both ends of the connected-in-series arrangement. It is illustrated in FIGS. 19 and 20. FIG. 19 is an equivalent circuit view illustrating the NAND type MRAM; FIG. 20 is a sectional view illustrating the layout of one memory cell block (for example, a memory cell block 26) in the equivalent circuit illustrated in FIG. 19. In FIG. 19, reference numerals 30, 32, 34, and 36 respectively denote magnetic resistive elements that will serve as memory carriers; reference numerals 31, 33, 35, and 37 respectively denote cell selection transistors that select their corresponding magnetic resistive elements; WL0 to WL3 denote word lines that supply gate control signals for the cell selection transistors; a reference numeral 38 denotes a selection transistor for selecting the memory block; and SS0 and SS1 each denote a control gate signal for the selection transistor. In FIG. 20, the same portions as those in FIG. 19 are denoted by like reference symbols. Incidentally, the magnetic resistive element that are represented by the reference numerals 30, 32, 34, and 36 are each a magnetic tunnel junction (MTJ=Magnetic Tunnel Junction) element; and reference numerals 46 to 49 are each a programming word line. Writing data into the MTJ element is executed by causing an electric current to flow into the programming word line to generate a magnetic field in the neighborhood of it and, using this magnetic field, inverting the magnetic moment of a free-magnetic-body layer provided within the MTJ element.
In the above-described NAND type cell array structure, by the cell selection transistors' 31, 33, 35, and 37 being connected in series, two adjoining of them can share the source/drain region. Therefore, as in the case of the NAND type flash EEPROM, it is possible to greatly decrease the memory size per bit. For comparison, in FIGS. 21 and 22, there are illustrated an equivalent circuit of a so-called NOR type magnetic random access memory (NOR type MRAM) using a magnetic resistive element, in which there is adopted no serial structure for memory cells such as that illustrated in FIGS. 19 and 20, and a sectional view that sections the layout of an elemental structure thereof. In FIG. 21, a reference numeral 49 denotes a magnetic resistive element, a reference numeral 50 denotes a cell selection transistor, a reference numeral 51 denotes a global bit line GBL, a reference numeral 52 denotes a local bit line LBL, a reference numeral 53 denotes a selection transistor for selecting a memory block 48, WL0 to WL3 denote word lines, and SS0 and SS1 denote control gate signals for the selection transistors. In FIG. 22, the same portions as those in FIG. 21 are denoted by like reference numerals or symbols. Here, as in the case of FIG. 20, a reference numeral 49 denotes a MTJ element while a reference numeral 66 denotes a programming word line. Comparing with FIG. 20, in FIG. 22, it is seen that there is the need to use contacts 67 for applying an earth potential to the source electrode of the cell selection transistor as well as separation regions 68 for making separation between the cell selection transistors. Like this, in the NAND type cell construction illustrated in FIGS. 19 and 20, it is possible to suppress the increase in the chip area relative to the memory cell array, such as that illustrated in FIGS. 21 and 22, in which the memory cell having a magneto-resistive element and a transistor connected in series with respect thereto is connected to the bit line.
As stated before, in the NAND type MRAM, each of the magneto-resistive elements 30, 32, 34, and 36 connected in parallel to the cell selection transistors is constructed using a magnetic tunnel junction (MTJ) element that is comprised of, for example, a ferromagnetic layer/insulating layer/ferromagnetic layer (for example, NiFe/AlO/NiFe). And, in this case, the resistance value varies depending on whether the direction of the spin in the ferromagnetic layer is parallel or contra-parallel. In a case where the size of the MTJ element is, for example, 0.4 μm×0.8 μm, the resistance value is approximately 10 kΩ, and the rate of change in resistance (the MR ratio=Magneto-resistance Ratio that is expressed as the ratio between the value of the low resistance and (the value of the high resistance−the value of the low resistance)), when converted in percentage, is approximately 30% or so.
The data programming/erasing operation is performed by inverting the direction of the spin in one ferromagnetic layer called “a free layer” using a magnetic field that generates by causing an electric current to flow into the programming word lines 46, 47, 48, and 49 and into the bit line 29. The programming/erasing speed is as fast as given in nano-seconds because of the magnetization direction's being inverted.
The reading operation is performed as follows. When explaining using FIG. 19 or 20, a voltage of Vcc is applied to the bit line 29 that is to be selected; a voltage of Vcc is applied to the selection gate SS0 that is connected to the memory cell that is to be selected; a voltage of Vss (=0V) is applied to the selected word line WL2; and a voltage of Vcc is applied to the unselected word lines WL. The voltage of Vcc is applied to the bit-line side of the magnetic resistive element 32 and the voltage of Vss is applied to the source side of it, thereby reading the resistance value of the magnetic resistive element 32.
However, as illustrated in FIG. 20, since a wiring layer 100 is disposed between the bit line and the magnetic resistive element, the distance between the bit line 29 and the magnetic resistive elements 32, 34, 36, and 38 gets increased relative to the distance between the bit line 52 and magnetic resistance element 49 of the memory array of the NOR type MRAM illustrated in FIGS. 21 and 22. Resultantly, when performing programming/erasing operations for data, the amount of electric current that is caused to flow into the bit line 29 becomes relatively large compared to that in the case of the NOR type MRAM. Therefore, in the NAND type MRAM, the electro-migration problem in the bit line arises. Namely, since the intensity of the magnetic field that generates around the bit line weakens depending on the distance that is relevant, to compensate for that the necessity of causing a larger amount of current to flow into the bit line comes up. This may become a factor to cause the occurrence of the migration problem.
As has been described above, the memory array using the NAND type memory cell units has, in addition of the contact with the bit line, the merit of the source line's being shared by adjoining two of the connected-in-series memory cells. Therefore, it is possible to greatly reduce the memory size per bit and to suppress the increase in the chip area. Considering the above, this memory array is very advantageous so long as the story is concerned with the high level of integration. However, in case of the NAND type flash EEPROM, the programming/erasing length of time is as large as given in milliseconds while, on the other hand, in case of the NAND type MRAM, it has the problem that a large amount of electric current becomes necessary.